Digital Electronic/Circuits Questions & Answers for entrance exams on “Realisation of one Flip-flop using other Flip-flops”.
1. To realise one flip-flop using another flip-flop along with a combinational circuit, known as ____________
A. PREVIOUS state decoder
B. NEXT state decoder
C. MIDDLE state decoder
D. PRESENT state decoder
Answer: B
Clarification: To realise one flip-flop using another flip-flop along with a combinational circuit, known as NEXT state decoder which acts as like a flip-flop.
2. For realisation of JK flip-flop from SR flip-flop, the input J and K will be given as ___________
A. External inputs to S and R
B. Internal inputs to S and R
C. External inputs to combinational circuit
D. Internal inputs to combinational circuit
Answer: A
Clarification: If a JK Flip Flop is required, the inputs are given to the combinational circuit and the output of the combinational circuit is connected to the inputs of the actual flip flop. So, J and K will be given as external inputs to S and R. As SR flip-flop have invalid state and JK flip-flop don’t.
3. For realisation of JK flip-flop from SR flip-flop, if J=0 & K=0 then the input is ___________
A. S=0, R=0
B. S=0, R=X
C. S=X, R=0
D. S=X, R=X
Answer: B
Clarification: If J=0 & K=0, the output will be as: Q(n)=0, Q(n+1)=0 and it is fed into both the AND gates which results as S=0 & R=X(i.e. don’t care).
4. For realisation of JK flip-flop from SR flip-flop, if J=1, K=0 & present state is 0(i.e. Q(n)=0) then excitation input will be ___________
A. S=0, R=1
B. S=X, R=0
C. S=1, R=0
D. S=1, R=1
Answer: C
Clarification: If J=1, K=0 & present state is 0(i.e. Q(n)=0) then next state will be 1 which results excitation inputs as S=1 & R=0.
5. For realisation of SR flip-flop from JK flip-flop, the excitation input will be obtained from ___________
A. S and R
B. R input
C. J and K input
D. D input
Answer: C
Clarification: It is the reverse process of SR flip-flop to JK flip-flop. So, for realisation of SR flip-flop from JK flip-flop, the excitation input will be obtained from J and K.
6. For realisation of SR flip-flop from JK flip-flop, if S=1, R=0 & present state is 0 then next state will be ___________
A. 1
B. 0
C. Don’t care
D. Toggle
Answer: A
Clarification: For JK flip-flop to SR flip-flop, if S=1, R=0 & present state is 0 then next state will be 1 because next stage is complement of present stage.
7. For realisation of SR flip-flop from JK flip-flop, if S=1, R=0 & present state is 0 then the excitation input will be ___________
A. J=1, K=1
B. J=X, K=1
C. J=1, K=X
D. J=0, K=0
Answer: C
Clarification: For realisation of SR flip-flop from JK flip-flop, if S=1, R=0 & present state is 0 then the excitation input will be J=1, K=X.
8. The K-map simplification for realisation of SR flip-flop from JK flip-flop is ___________
A. J=1, K=0
B. J=R, K=S
C. J=S, K=R
D. J=0, K=1
Answer: C
Clarification: The K-map simplification for realisation of SR flip-flop from JK flip-flop is given by: J=S, K=R.
9. For realisation of D flip-flop from SR flip-flop, the external input is given through ___________
A. S
B. R
C. D
D. Both S and R
Answer: C
Clarification: For realisation of D flip-flop from SR flip-flop, S and R are the actual inputs of the flip flop which is connected together via NOT gate and it is called external input as D.
10. For D flip-flop to JK flip-flop, the characteristics equation is given by ___________
A. D=JQ(p)’+Q(p)K’
B. D=JQ(p)’+KQ(p)’
C. D=JQ(p)+Q(p)K’
D. D=J’Q(p)+Q(p)K
Answer: A
Clarification: A characteristic equation is needed when a specific gate requires a specific output in order to satisfy the truth table. For D flip-flop to JK flip-flop, the characteristics equation is given by D=JQ(p)’+Q(p)K’.
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