VLSI Multiple Choice Questions on “Rules for Proper Design”.
1. The Zp.u./Zp.d. ratio for nMOS inverter is
A. 4:1
B. 3:1
C. 1:4
D. 1:3
Answer: A
Clarification: For nMOS inverters the Zp.u./Zp.d. ratio is 4:1 when driven from another inverter and 8:1 when driven through one or more pass transistors.
2. The impedance ratio for pseudo-nMOS is
A. 4:1
B. 3:1
C. 1:4
D. 1:3
Answer: B
Clarification: For pseudo-nMOS, the Zp.u./Zp.d. ratio is 3:1 and for CMOS 1:1 ratio is required for minimum area.
3. What is the value for peripheral capacitance for 5 micron technology?
A. 4 x 10(-4) pf/µm2
B. 5 x 10(-4) pf/µm2
C. 8 x 10(-4) pf/µm2
D. 12 x 10(-4) pf/µm2
Answer: C
Clarification: Peripheral capacitance is the side wall capacitance. Peripheral capacitance of 5 micron technology is 8 x 10(-4) pf/µm2.
4. 1 square Cg is ___________ of MOS transistor.
A. gate to source capacitance
B. gate to drain capacitance
C. source to drain capacitance
D. gate to channel capacitance
Answer: D
Clarification: 1 square Cg is defined as the gate to channel capacitance of a MOS transistor having standard feature size (W=L).
5. What is the delay value Ʈ for 1.2 micron technology?
A. 0.1 nsec
B. 0.12 nsec
C. 0.046 nsec
D. 0.064 nsec
Answer: C
Clarification: The delay Ʈ is the time constant and for 1.2 micron technology its value is 0.046 nsec.
6. Which is used to increase Ʈ?
A. parasitic capacitance
B. peripheral capacitance
C. area capacitance
D. load capacitance
Answer: A
Clarification: Circuit wiring and parasitic capacitance must be allowed to increase the value of Ʈ by the factor of 2 or 3.
7. The inverter pair delay is given by
A. (Zp.u./Zp.d.)Ʈ
B. (1+ Zp.u./Zp.d.)Ʈ
C. (1+ Zp.u./Zp.d.)Ʈ
D. (1+ Ʈ)Zp.u./Zp.d.
Answer: B
Clarification: The inverter delay is given by (1+ Zp.u./Zp.d.)Ʈ. The inverter pair delay for CMOS is 7Ʈ.
8. The number of stages N is given by
A. ln(y)/ln(f)
B. ln(f)/ln(y)
C. ln(2y)/ln(f)
D. ln(y)/ln(2f)
Answer: A
Clarification: To calculate the value for N, where N inverters are cascaded, each one of which is larger than the preceding stage by a width factor f the formula used is ln(y)/ln(f).
9. If f assumes the value e then delay is
A. maximized
B. minimized
C. does not change
D. doubled
Answer: B
Clarification: Total delay is minimized if f assumes the value of e which is the base of the natural logarithm. This applies to both nMOS and CMOS.
10. Propogation delay is given by
A. nrcƮ
B. n2rcƮ
C. nr2cƮ
D. n2cƮ
Answer: B
Clarification: Propogation delay through cascaded pass transistors or transmission gate can be given as n2rcƮ.
11. Using _____ long wires are possible.
A. silicide
B. metal
C. polysilicon
D. diffusion
Answer: A
Clarification: Using silicide, reasonable long wires are possible. It is a modest RC product. Silicides are used in place of polysilicon in some nMOS processes.
12. One pass transistor can be driven through output of another.
A. true
B. false