Computer Organization and Architecture Multiple Choice Questions on “Cache Miss and Hit”.
1. The main memory is structured into modules each with its own address register called ______
a) ABR
b) TLB
c) PC
d) IR
Answer: a
Clarification: ABR stands for Address Buffer Register.
2. When consecutive memory locations are accessed only one module is accessed at a time.
a) True
b) False
Answer: a
Clarification: In a modular approach to memory structuring only one module can be accessed at a time.
3. In memory interleaving, the lower order bits of the address is used to _____________
a) Get the data
b) Get the address of the module
c) Get the address of the data within the module
d) None of the mentioned
Answer: b
Clarification: To implement parallelism in data access we use interleaving.
4. The number successful accesses to memory stated as a fraction is called as _____
a) Hit rate
b) Miss rate
c) Success rate
d) Access rate
Answer: a
Clarification: The hit rate is an important factor in performance measurement.
5. The number failed attempts to access memory, stated in the form of a fraction is called as _________
a) Hit rate
b) Miss rate
c) Failure rate
d) Delay rate
Answer: b
Clarification: The miss rate is a key factor in deciding the type of replacement algorithm.
6. In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are incremented by one, when _____ occurs.
a) Delay
b) Miss
c) Hit
d) Delayed hit
Answer: b
Clarification: Miss usually occurs when the memory block required is not present in the cache.
7. In LRU, the referenced blocks counter is set to’0′ and that of the previous blocks are incremented by one and others remain same, in the case of ______
a) Hit
b) Miss
c) Delay
d) None of the mentioned
Answer: a
Clarification: If the referenced block is present in the memory it is called as hit.
8. If hit rates are well below 0.9, then they’re called as speedy computers.
a) True
b) False
Answer: b
Clarification: It has to be above 0.9 for speedy computers.
9. The extra time needed to bring the data into memory in case of a miss is called as __________
a) Delay
b) Propagation time
c) Miss penalty
d) None of the mentioned
Answer: c
Clarification: None.
10. The miss penalty can be reduced by improving the mechanisms for data transfer between the different levels of hierarchy.
a) True
b) False
Answer: a
Clarification: The extra time needed to bring the data into memory in case of a miss is called as miss penalty.