Computer Organization and Architecture Multiple Choice Questions on “Single BUS Organisation”.
1. The CPU is also called as ________
a) Processor hub
b) ISP
c) Controller
d) All of the mentioned
Answer: b
Clarification: ISP stands for Instruction Set Processor.
2. A common strategy for performance is making various functional units operate parallelly.
a) True
b) False
Answer: a
Clarification: By parallelly accessing data we can have a pipelined processor.
3. The PC gets incremented _____________
a) After the instruction decoding
b) After the IR instruction gets executed
c) After the fetch cycle
d) None of the mentioned
Answer: c
Clarification: The PC always points to the next instruction to be executed.
4. Which register in the processor is single directional?
a) MAR
b) MDR
c) PC
d) Temp
Answer: a
Clarification: The MAR is single directional as it just takes the address from the processor bus and passes it to the external bus.
5. The transparent register/s is/are __________
a) Y
b) Z
c) Temp
d) All of the mentioned
Answer: d
Clarification: These registers are usually used to store temporary values.
6. Which register is connected to the MUX?
a) Y
b) Z
c) R0
d) Temp
Answer: a
Clarification: The MUX can either read the operand from the Y register or increment the PC.
7. The registers, ALU and the interconnecting path together are called as ______
a) Control path
b) Flow path
c) Data path
d) None of the mentioned
Answer: c
Clarification: None.
8. The input and output of the registers are governed by __________
a) Transistors
b) Diodes
c) Gates
d) Switches
Answer: d
Clarification: None.
9. When two or more clock cycles are used to complete data transfer it is called as ________
a) Single phase clocking
b) Multi-phase clocking
c) Edge triggered clocking
d) None of the mentioned
Answer: b
Clarification: This is basically used in systems without edge-triggered flip flops.
10. ________ signal is used to show complete of memory operation.
a) MFC
b) WMFC
c) CFC
d) None of the mentioned
Answer: a
Clarification: MFC stands for Memory Function Complete.