Computer Organization and Architecture Multiple Choice Questions on “Static Memories”.
1. The duration between the read and the mfc signal is ______
a) Access time
b) Latency
c) Delay
d) Cycle time
Answer: a
Clarification: The time between the issue of a read signal and the completion of it is called memory access time.
2. The minimum time delay between two successive memory read operations is ______
a) Cycle time
b) Latency
c) Delay
d) None of the mentioned
Answer: a
Clarification: The Time taken by the cpu to end one read operation and to start one more is cycle time.
3. MFC is used to _________
a) Issue a read signal
b) Signal to the device that the memory read operation is complete
c) Signal the processor the memory operation is complete
d) Assign a device to perform the read operation
Answer: c
Clarification: The MFC stands for memory Function Complete.
4. __________ is the bottleneck, when it comes computer performance.
a) Memory access time
b) Memory cycle time
c) Delay
d) Latency
Answer: b
Clarification: The processor can execute instructions faster than they’re fetched, hence cycle time is the bottleneck for performance.
5. The logical addresses generated by the cpu are mapped onto physical memory by ____________
a) Relocation register
b) TLB
c) MMU
d) None of the mentioned
Answer: c
Clarification: The MMU stands for memory management unit, which is used to map logical address onto the physical address.
6. VLSI stands for ___________
a) Very Large Scale Integration
b) Very Large Stand-alone Integration
c) Volatile Layer System Interface
d) None of the mentioned
Answer: a
Clarification: None.
7. The cells in a row are connected to a common line called ______
a) Work line
b) Word line
c) Length line
d) Principle diagonal
Answer: b
Clarification: This means that the cell contents together form one word of instruction or data.
8. The cells in each column are connected to ______
a) Word line
b) Data line
c) Read line
d) Sense/ Write line
Answer: d
Clarification: The cells in each column are connected to the sense/write circuit using two bit lines and which is in turn connected to the data lines.
9. The word line is driven by the _____
a) Chip select
b) Address decoder
c) Data line
d) Control line
Answer: b
Clarification: None.
10. A 16 X 8 Organisation of memory cells, can store upto _____
a) 256 bits
b) 1024 bits
c) 512 bits
d) 128 bits
Answer: d
Clarification: It can store upto 128 bits as each cell can hold one bit of data.
11. A memory organisation that can hold upto 1024 bits and has a minimum of 10 address lines can be organized into _____
a) 128 X 8
b) 256 X 4
c) 512 X 2
d) 1024 X 1
Answer: d
Clarification: All the others require less than 10 address bits.
12. Circuits that can hold their state as long as power is applied is _______
a) Dynamic memory
b) Static memory
c) Register
d) Cache
Answer: b
Clarification: None.
13. The number of external connections required in 16 X 8 memory organisation is _____
a) 14
b) 19
c) 15
d) 12
Answer: a
Clarification: In the 14, 8-data lines,4-address lines and 2 are sense/write and CS signals.
14. The advantage of CMOS SRAM over the transistor one’s is _________
a) Low cost
b) High efficiency
c) High durability
d) Low power consumption
Answer: d
Clarification: This is because the cell consumes power only when it is being accessed.
15. In a 4M-bit chip organisation has a total of 19 external connections.then it has _______ address if 8 data lines are there.
a) 10
b) 8
c) 9
d) 12
Answer: c
Clarification: To have 8 data lines and 19 external connections it has to have 9 address lines(i.e 512 x 8 organisation).